Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor memory device for reliably performing operations according to a burst length.
Semiconductor memory devices including a double data rate synchronous dynamic random access memory (DDR SDRAM) contain a plurality of memory cells and perform read/write operations according to instructions from a chipset. The semiconductor memory devices stores a data signal in a memory cell corresponding to an address input from the chipset in response a write operation instruction and outputs a data signal stored in a memory cell corresponding to an address input from the chipset in response a read operation instruction.
In order to improve the efficiency of the read and write operations of the semiconductor memory device, it is possible to set the number of data signals consecutively inputted or outputted through a single input/output (I/O) pad. In this disclosure, the number of the data signals consecutively inputted or outputted through the single I/O pad is referred to as “the burst length.” For example, four data signals are consecutively inputted or outputted through the single I/O pad when the burst length is set to 4 and eight data signals are consecutively inputted or outputted through the single I/O pad when the burst length is set to 8. Generally, the burst length is defined by a signal externally inputted and the semiconductor memory device consecutively inputs or outputs a number of data signals corresponding to the burst length in response to the signal.
FIG. 1 is a block diagram depicting a conventional semiconductor memory device.
The semiconductor memory device includes a shift unit 110 and a multiplex (MUX) unit 120. The shift unit 110 includes a plurality of D-flip flips (DFF) and shifts a burst length information signal INF_BL in response to an external clock signal D_CLK_EXT. The MUX unit 120 selects one of the burst length information signal INF_BL and outputs QR<0:4> of the shift unit 110 in response to column access strobe (CAS) latency signals CL<5:11> and outputs the selected one as a burst length pulse signal PUL_BL.
Herein, the burst length information signal INF_BL defines the burst length of the semiconductor memory device. For example, the burst length of the semiconductor memory device is set to 4 when the burst length information signal INF_BL has a logic low level and the burst length of the semiconductor memory device is set to 8 when the burst length information signal INF_BL has a logic high level.
FIG. 2 is a timing waveform illustrating an operation of the semiconductor memory device shown in FIG. 1.
The semiconductor memory device determines the burst length by combining the burst length pulse signal PUL_BL and a latency signal LTC. In detail, the semiconductor memory device determines the burst length based on a logic level of the burst length pulse signal PUL_BL at an active period of the latency signal LTC. For example, the semiconductor memory device operates according to the burst length of 4 when the burst length pulse signal PUL_BL has a logic low level at the active period of the latency signal LTC and the semiconductor memory device operates according to the burst length of 8 when the burst length pulse signal PUL_BL has a logic high level at the active period of the latency signal LTC. For ensuring a correct operation of the semiconductor memory device, the active period of the latency signal LTC should be placed within a valid window T1 of the burst length pulse signal PUL_BL.
The latency signal LTC controls a data output timing of the semiconductor memory device and the active period of the latency signal LTC is determined based on the CAS latency signal CL<5:11> in synchronism with an internal clock signal. The internal clock signal is outputted from a delay locked loop (DLL) circuit.
As an operational frequency of the semiconductor memory device becomes higher, it becomes difficult to place the active period of the latency signal LTC within the valid window T1 of the burst length pulse signal PUL_BL. This problem is mainly caused because the burst length pulse signal PUL_BL is generated in synchronism with the external clock signal D_CLK_EXT and the latency signal LTC is generated in synchronism with the internal clock signal.
Accordingly, the semiconductor memory device shown in FIG. 2 performs erroneous operations based on incorrect burst length information as the operational frequency increases. This causes the deterioration of reliability of the semiconductor memory device.